Semiconductor device and method of manufacturing same

ABSTRACT

Disclosed is a semiconductor device which has a wiring structure including a small-width wiring connected to a large-width wiring through a connection hole or holes formed in an inter-layer insulation film and in which reliability of wiring can be enhanced by regulating the number of the connection hole or holes and the location(s) of the connection hole or hole. The semiconductor device includes first wirings ( 21 ), ( 22 ), an inter-layer insulation film (not shown) covering the first wirings ( 21 ), ( 22 ), second wirings ( 31 ), ( 33 ) connected to the first wirings ( 21 ), ( 22 ) through the connection holes formed in the inter-layer insulation film, the first wirings ( 21 ), ( 22 ) being formed to be larger in width than the second wirings ( 31 ), ( 33 ), wherein a plurality of the connection holes ( 41 ), ( 42 ) and connection holes ( 43 ) to ( 45 ) are provided, and the plurality of the connection holes ( 41 ), ( 42 ), ( 43 ) to ( 45 ) are disposed at intervals between the connection holes ( 41 ), ( 42 ) and between the connection holes ( 43 ) to ( 45 ) within the range of from 1 to 18 times the connection hole diameter.

TECHNICAL FIELD

The present invention relates to a semiconductor device including amulti-layer wiring, and particularly to a semiconductor device includinga multi-layer wiring in which a large-width wiring and a small-widthwiring are connected between different wiring layers.

BACKGROUND ART

The number of connection holes for connection between different wiringlayers is determined according to the widths of the wirings to beconnected and the current to be passed through the wiring formed in theconnection holes. However, in the case where a large-width wiring (forexample, a wiring not less than 1 μm in width) and a small-width wiring(for example, a wiring about 0.14 μm in width) are connected, forexample, where a small-width wiring is led out from a power supply wirefor potential fixation, a single connection hole is used for theconnection.

The material for forming the wiring layers and the material used forinsulation between the wiring layers have come to changed to alow-resistance wiring material represented by copper (Cu) and to alow-dielectric-constant insulating material represented by polyarylether-based resins (for example, FLARE produced by Allied Signal, SiLKproduced by Dow Chemical, VE produced by Schumacher, and the like areknown), silicon oxycarbide (SiOC) and the like, for coping with thewiring delay arising from scale-down of wiring pitch.

In addition, it has been reported that Cu as a low-resistance materialis more excellent in electro-migration resistance than aluminum (Al)which has been widely used as a wiring material. In the case of forminga small-width wiring by use of Cu, however, it is difficult to use a dryetching method, since there has not been found any dry etching gassuitable for etching Cu at a high selectivity ratio relative to theinsulating film serving as a base material. Therefore, it is a generalpractice to form a buried wiring by a trench wiring method (for example,the Damascene process). Particularly, a method of filling (or burying)connection holes and a wiring layer simultaneously (for example, thedual Damascene process) is considered to be a promising method from theviewpoints of enlarging the register margin in lithography andshortening the processing steps.

As has been mentioned above, the wiring material has been changed fromAl to Cu. As shown in FIG. 12, by using a pattern in which a singleconnection hole 125 was provided for connecting a small-width wiring 123to a large-width wiring 121 satisfying the relationship of (wiringwidth)/(connection hole diameter)≧7 and a single connection hole 126 wasprovided for connecting a small-width wiring 124 to a large-width wiring122 satisfying the relationship of (wiring width)/(connection holediameter)≧7, a high-temperature standing test (the specimen was left tostand at 225° C. for 500 hr) as a wiring reliability evaluation wascarried out.

As a result of analysis of a defective portion upon the test, losing ofCu was confirmed on the side of the large-width wiring 121 beneath theconnection hole 125, as shown in FIG. 13. In addition, as shown in FIG.14, a similar phenomenon was confirmed also in the case where thelarge-width wiring 121 was disposed on the upper side of the connectionhole 125; in this case, losing of Cu was generated in the inside of theconnection hole 125. The mechanism of these defects has not yet beenelucidated. It is supposed, however, that under the influences of astress due to a difference in thermal expansion coefficient between thewiring and the insulating film and a stress of the insulating filmitself, migration of Cu was caused at the wiring beneath the connectionhole, resulting in the losing of Cu. Besides, in view of the fact thatdependency on wiring width is seen, it is considered that the phenomenonwas caused also by the influence of volumetric shrinkage attendant oncrystal growth at the wiring.

DISCLOSURE OF INVENTION

The present invention pertains to a semiconductor device which has beendevised in order to solve the above-mentioned problems in the relatedart.

In accordance with the present invention, there is provided asemiconductor device including a first wiring, an inter-layer insulationfilm covering the first wiring, a connection hole or holes formed in theinter-layer insulation film so as to reach the first wiring, and asecond wiring connected to the first wiring through the connection holeor holes, the first wiring or the second wiring being formed to belarger in width than the other wiring, wherein a plurality of theconnection holes are provided. The plurality of the connection holes areso disposed that the spacing between the connection holes is in therange of 1 to 18 times the diameter of the connection holes.

In the above semiconductor device, the first wiring or the second wiringis formed to be larger in width than the other wiring, but the provisionof the plurality of connection holes lowers the defect generationprobability. This is because the increase in the number of connectionholes ensures that where, for example, two connection holes are used forconnection between the wirings, breakage of electric conduction wouldnot be generated unless defects are generated simultaneously at the twoconnection holes. Thus, the provision of a plurality of connection holesis effective for preventing the breakage trouble.

Where a plurality of connection holes are provided, it is desired thatthe connection holes are disposed within a predetermined interval. FIG.9 shows the defect generation rate (hereinafter referred to as fractiondefective) upon a high-temperature standing test (the specimen is leftto stand at 225° C. for 500 hr) against the ratio of the connection holeinterval to the connection hole diameter. It is seen that where theplurality of connection holes are disposed at a connection hole intervalwithin the range of from 1 to 18 times the connection hole diameter, asshown in FIGS. 8A and 8B, the fraction defective is zero (0). In view ofthis, it is desirable that the plurality of connection holes aredisposed at a connection hole interval within the range of from 1 to 18times the connection hole diameter.

In accordance with the present invention, there is provided asemiconductor device including a first wiring, an inter-layer insulationfilm covering the first wiring, a connection hole or holes formed in theinter-layer insulation film so as to reach the first wiring, and asecond wiring connected to the first wiring through the connection holeor holes, the first wiring or the second wiring being formed to belarger in width than the other wiring, wherein the minimum requirednumber of the connection hole or holes formed is one where W/V<7, is twowhere 7≦W/V<70, and is three where 70≦W/V, where W is the width of thelarge-width wiring, and V is the connection hole diameter.

In the above semiconductor device, the volumetric shrinkage portions ofvolumetric shrinkage due to crystal growth at the wiring, which isconsidered to be a cause of the defect to be solved by the presentinvention, is considered to be concentrated on the connection hole, butthe above-described optimization of the number of the connection hole orholes makes it possible to absorb the volumetric shrinkage amount (whichdepends on the wiring width), and the number of the connection hole orholes required for conduction is found out.

FIG. 10 shows the relationship between the ratio of wiring width toconnection hole diameter (W/V) at the first wiring larger in width thanthe second wiring in a wiring structure formed by simultaneously fillingup the connection hole or holes and wiring trenches with Cu, and thefraction defective upon a high-temperature standing test (the specimenis left to stand at 225° C. for 500 hr) taking the number of connectionhole or holes as a parameter. As shown in FIG. 10, when the ratio ofwiring width to connection hole diameter (W/V) exceeds 7, a defect isgenerated upon the high-temperature standing test where a singleconnection hole is provided, but the generation of the defect can berestrained by providing two connection holes. In addition, when thewiring width becomes further larger and the ratio of wiring width toconnection hole diameter (W/V) exceeds 70, the defect is generated evenwhere two connection holes are provided, but the defect can be obviatedby providing three connection holes. Thus, the defect upon thehigh-temperature standing test can be obviated by providing a pluralityof connection holes according to the wiring width.

In accordance with the present invention, there is provided asemiconductor device including a first wiring, an inter-layer insulationfilm covering the first wiring, a connection hole or holes formed in theinter-layer insulation film so as to reach the first wiring, and asecond wiring connected to the first wiring through the connection holeor holes, the first wiring or the second wiring being formed to belarger in width than the other wiring, wherein the device includes aleader wiring formed in continuity with the large-width wiring andsmaller in width than the large-width wiring, and the connection hole orholes are formed in the inter-layer insulation film so as to reach theleader wiring. The semiconductor device satisfies the relation ship ofWs/V<7, where Ws is the width of the leader wiring, and V is theconnection hole diameter, and the device satisfies the relationship ofW/S<143 μm⁻¹, where S is the area occupied by the leader wiring portionranging from the large-width wiring to the location of the connectionhole, and W is the width of the large-width wiring satisfying therelationship of W/V≧7.

In the above semiconductor device, as a countermeasure for coping withthe problem that the connection hole or hole cannot be disposedaccording to the wiring width, the connection hole is connected to theleader wiring portion formed in continuity with the large-width wiringand smaller in width than the large-width wiring, and, therefore, theproblem which has been generated with the large-width wiring portion canbe obviated. FIGS. 11A and 11B show the fraction defective upon thehigh-temperature standing test (the specimen is left to stand at 225° C.for 500 hr) against W/S, where W is the width of the large-width wiring,and S is the area of the leader wiring portion ranging from thelarge-width wiring to the location of the connection hole. The area Scan be determined as Ws×Ls, where Ws is the width of the leader wiringportion formed in continuity with the large-width wiring and smaller inwidth than the large-width wiring, and Ls the distance from thelarge-width wiring to the location of the connection hole along theleader wiring portion.

As shown in FIGS. 11A and 11B, by a setting that W/S≦143 μm⁻¹, thegeneration of the defect can be obviated even where only one connectionhole is provided. In this case, it is necessary that the width Ws of theleader wiring portion smaller in width than the large-width wiringsatisfies the relationship of Ws/V<7. The reason for this is the same ashas been described above referring to FIG. 10.

In accordance with the present invention, there is provided a method ofmanufacturing a semiconductor device, including the steps of: forming afirst wiring; forming an inter-layer insulation film on the firstwiring; providing the inter-layer insulation film with a connection holeor holes reaching the first wiring; and forming on the inter-layerinsulation film a second wiring connected to the first wiring throughthe inside of the connection hole or holes, the first wiring or thesecond wiring being formed to be larger in width than the other wiring,wherein a plurality of the connection holes reaching the large-widthwiring are provided. The plurality of the connection holes are disposedat a connection hole interval within the range of from 1 to 8 times theconnection hole diameter.

In the above method of manufacturing a semiconductor device, eventhrough the first wiring or the second wiring is formed to be larger inwidth than the other wiring, the provision of the plurality of theconnection holes makes it possible to manufacture a semiconductor devicein which the probability of defect generation at the connection holeportions is lowered. This is because the increase in the number ofconnection holes ensures that where, for example, at least twoconnection holes are provided for connection between the wirings,breakage of electric conduction would not be generated unless defectsare simultaneously generated at two connection holes. Thus, formation ofa plurality of connection holes is effective for preventing the breakagetrouble.

In disposing the plurality of connection holes, it is desirable todispose the connection holes within a predetermined connection holeinterval. The reason is the same as has been described above referringto FIG. 9.

In accordance with the present invention, there is provided a method ofmanufacturing a semiconductor device, including the steps of: forming afirst wiring; forming an inter-layer insulation film on the firstwiring; providing the inter-layer insulation film with a connection holeor holes reaching the first wiring; and forming on the inter-layerinsulation film a second wiring connected to the first wiring throughthe inside of the connection hole or holes, the first wiring or thesecond wiring being formed to be larger in width than the other wiring,wherein the number of the connection hole or holes formed is one whereW/V<7, is two where 7≦W/V<70, and is three where 70≦W/V, where W is thewidth of the large-width wiring, and V is the connection hole diameter.

In the above method of manufacturing a semiconductor device, the numberof the connection hole or holes formed is one where W/V<7, is two where7≦W/V<70, and is three where 70≦W/V, where W is the width of thelarge-width wiring, and V is the connection hole diameter. Therefore, ashas been described above referring to FIG. 10, the provision of theplurality of connection holes according to the wiring width makes itpossible to obviate the defect upon the high-temperature standing test.

In accordance with the present invention, there is provided a method ofmanufacturing a semiconductor device, including the steps of: forming afirst wiring; forming an inter-layer insulation film on the firstwiring; providing the inter-layer insulation film with a singleconnection hole reaching the first wiring; and forming on theinter-layer insulation film a second wiring connected to the firstwiring through the inside of the connection hole, the first wiring orthe second wiring being formed to be larger in width than the otherwiring, wherein a leader wiring smaller in width than the large-widthwiring is formed together with the large-width wiring in continuity withthe large-width wiring, and the other wiring is formed on theinter-layer insulation film so as to be connected to the leader wiringthrough the inside of the connection hole. Further, the method satisfiesthe relationship of Ws/V<7, where Ws is the width of the leader wiring,and V is the connection hole diameter, and the method satisfies therelationship of W/S<143 μm⁻¹, where S is the area occupied by the leaderwiring portion ranging from the large-with wiring to the location of theconnection hole, and W is the width of the large-width wiring satisfyingthe relationship of W/V≧7.

In the above method of manufacturing a semiconductor device, thelarge-width wiring is provided with the leader wiring formed incontinuity with the large-width wiring and smaller in width than thelarge-width wiring, and the connection hole is connected to the leaderwiring portion, so that the problem which would otherwise be generatedat the large-width wiring portion is obviated. In addition, since Ws/V<7is satisfied and W/V<143 μm⁻¹ is satisfied, the fraction defective uponthe high-temperature standing test against W/S becomes zero (0), as hasbeen described above referring to FIGS. 11A and 11B.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a wiring layout diagram showing a first embodiment of thesemiconductor device according to the present invention.

FIG. 2 is a wiring layout diagram showing a second embodiment of thesemiconductor device according to the present invention.

FIG. 3 is a wiring layout diagram showing a modification of the secondembodiment of the semiconductor device according to the presentinvention.

FIG. 4 is a wiring layout diagram showing another modification of thesecond embodiment of the semiconductor device according to the presentinvention.

FIGS. 5A to 5C are manufacturing step sectional views for illustratingan embodiment of the method of manufacturing a semiconductor deviceaccording to the present invention.

FIGS. 6A and 6B are manufacturing step sectional views for illustratingan embodiment of the method of manufacturing a semiconductor deviceaccording to the present invention.

FIGS. 7A and 7B are manufacturing step sectional views for illustratingan embodiment of the method of manufacturing a semiconductor deviceaccording to the present invention.

FIGS. 8A and 8B are manufacturing step sectional views for illustratingan embodiment of the method of manufacturing a semiconductor deviceaccording to the present invention.

FIG. 9 is a diagram showing the relationship between fraction defectiveand the ratio of connection hole interval to connection hole diameter.

FIG. 10 is a diagram showing the relationship between the fractiondefective and the ratio (W/V) of first wiring width (W) to connectionhole diameter (V).

FIGS. 11A and 11B are diagrams showing the relationship between fractiondefective and the ratio (W/S) of first wiring width (W) to the area (S)of the leader wiring portion ranging from the first wiring to theconnection hole.

FIG. 12 is a wiring layout diagram showing a wiring connection structurein a semiconductor device according to the related art.

FIG. 13 is a schematic sectional view for illustrating the result of ananalysis of a defective portion.

FIG. 14 is a schematic sectional view for illustrating the result of ananalysis of a defective portion.

BEST MODE FOR CARRYING OUT THE INVENTION

Now, a first embodiment of the semiconductor device according to thepresent invention will be described, referring to a wiring layoutdiagram in FIG. 1. For simplicity of description, in the drawing, deviceregions, device isolation regions, inter-layer insulation films and thelike formed in or on a silicon substrate are omitted, and only wiringsare illustrated.

As shown in FIG. 1, first wirings 21, 22, 23, and 24 of a first wiringlayer are formed, for example in X direction, on a silicon substrate(not shown), with an insulation film (not shown) therebetween. The firstwirings 21 to 24 can be formed, for example, of copper, a copper alloy,aluminum or the like. Further, second wirings 31, 32, and 33 of a secondwiring layer are formed, for example in Y direction, on the first wiringlayer so as to cross the first wiring layer, with an inter-layerinsulation film (not shown) therebetween. The second wirings 31 to 33can be formed, for example, of copper, a copper alloy, aluminum or thelike.

In addition, the inter-layer insulation film formed between the firstwiring layer and the second wiring layer is provided with connectionholes 41 and 42 for connection between the first wiring 21 and thesecond wiring 31, is provided with connection holes 43, 44, and 45 forconnection between the first wiring 22 and the second wiring 33, isprovided with a connection hole 46 for connection between the firstwiring 23 and the second wiring 34, and is provided with a connectionhole 47 for connection between the first wiring 24 and the second wiring32. Each of the connection holes 41 to 47 is provided therein with anelectrically conductive connection portion. Each of the connection holes41 to 47 may be formed integrally with the relevant wiring, or may beformed separately from the relevant wiring. Here, each connection holeis assumed to be formed integrally with the relevant second wiring.Therefore, the connection portions are formed of a material similar tothat of the second wirings.

The first wirings 21 and 22 satisfy the relationship 7≦W1/V, where W1 isthe width of the first wirings, and V is the connection hole diameter,whereas the first wirings 23 and 24 satisfy the relationship W1/V<7,where W1 is the width of the first wirings, and V is the connection holediameter. The second wirings 31, 32, and 33 satisfy the relationshipW2/V<7, where W2 is the width of the second wirings, and V is theconnection hole diameter.

The plurality of the connection holes 41 and 42 are so disposed that theinterval between the connection holes 41 and 42 is within the range offrom 1 to 18 times the connection hole diameter V. Similarly, theconnection holes 43, 44, and 45 are also so disposed that the intervaltherebetween is within the range of from 1 to 18 times the connectionhole diameter V.

The minimum required number of the connection holes for the firstwirings is one where W/V<7, is two where 7≦W/V<70, and is three where70≦W/V, where W is the width of the first wiring, and V is theconnection hole diameter.

In the above semiconductor device, although the first wiring 21 islarger in width than the second wiring 31 and the first wiring 22 islarger in width than the second wiring 33, the provision of theplurality of the connection holes 41 to 45 leads to a lowering in theprobability of generation of defects. This is because the increase inthe number of connection holes ensures that where, for example, at leasttwo connection holes are provided for connection between the wirings,breakage of electric conduction would not be generated unless defectsare simultaneously generated at two connection holes. Thus, theprovision of a plurality of connection holes is effective for preventingthe breakage trouble.

As has been described above, where a plurality of connection holes areprovided, it is desirable that the connection holes are disposed withina predetermined interval. The reason is the same as has been describedabove referring to FIG. 9.

Besides, in the above semiconductor device, by optimizing the number ofthe connection holes, the volumetric shrinkage amount (which depends onthe wiring width) can be absorbed, and the number of connection holesrequired for conduction is found out. The reason is as has beendescribed above referring to FIG. 10. Namely, when the ratio W/V ofwiring width (W) to connection hole diameter (V) exceeds 7, the defectupon the high-temperature standing test is generated where a singleconnection hole is only provided, but the generation of the defect canbe restrained where two connection holes are provided. When the wiringwidth increases further and the ratio W/V of wiring width (W) toconnection hole diameter (V) exceeds 70, the defect is generated evenwhere two connection holes are provided, but the defect can be obviatedby providing three connection holes. In this way, the defect upon thehigh-temperature standing test can be obviated by providing a pluralityof connection holes according to the wiring width.

Next, a second embodiment of the semiconductor device according to thepresent invention will be described referring to a wiring layout diagramin FIG. 2. For simplicity of description, in the drawing, deviceregions, device isolation regions, inter-layer insulation films and thelike are omitted, and only wirings are illustrated. Besides, the samecomponent parts as those described referring to FIG. 1 are denoted bythe same symbols as used above.

As shown in FIG. 2, first wirings 21, 22, 23, and 24 of a first wiringlayer are formed, for example in X direction, on a silicon substrate(not shown), with an insulation film (not shown) therebetween. The firstwiring 21 is provided with a wiring 25 (hereinafter referred to as thenarrow wiring 25) which is formed in continuity or connection with thefirst wiring 21 and which is smaller in width than the first wiring 21.In addition, the first wiring 22 is provided with a wiring 26(hereinafter referred to as the narrow wiring 26) which is formed incontinuity or connection with the first wiring 22 and which is smallerin width than the first wiring 22. Further, second wirings 31, 32, and33 of a second wiring layer are formed, for example in Y direction, onthe first wiring layer so as to cross the first wiring layer, with aninter-layer insulation film (not shown) therebetween.

In addition, the inter-layer insulation film formed between the firstwiring layer and the second wiring layer is provided with a connectionhole 48 for connection between the narrow wiring 25 and the secondwiring 31, is provided with a connection hole 49 for connection betweenthe narrow wiring 26 and the second wiring 33, is provided with aconnection hole 46 for connection between the first wiring 23 and thesecond wiring 34, and is provided with a connection hole 47 forconnection between the first wiring 24 and the second wiring 32. Each ofthe connection holes 46 to 49 is provided therein with an electricallyconductive connection portion. Each of the connection holes 46 to 49 maybe formed integrally with the relevant wiring, or may be formedseparately from the relevant wiring. Here, it is assumed that eachconnection hole is formed integrally with the relevant wiring.

In the above wiring structure, let the wiring width of the narrowwirings 25 and 26 be Ws and let the diameter of the connection holes 48and 49 be V, then it is necessary to satisfy the relationship of Ws/V<7,and, let the width of the narrow wiring 25 be Ws and let the distancefrom the first wiring 21 to the location of the connection hole 48 alongthe narrow wiring 25 be Ls, then the area S occupied by the region ofthe narrow wiring 25 ranging from the first wiring 21 to the connectionhole 48 is Ws×Ls. Let the width of the first wiring 21 satisfying W/V≧7be W, it is necessary to fulfill the relationship of W/S<143 μm⁻¹. Forthe narrow wiring 26, also, it is necessary to satisfy the relationshipof W/V<143 μm⁻¹, where S is the area occupied by the region of thenarrow wiring 26 ranging from the second wiring 22 to the connectionhole 49, and W is the width of the first wiring 22 satisfying W/V≧7.

According to the above constitution, the second wiring can be connectedto the first wiring which satisfies W/V≧7, via the single connectionhole.

Besides, while the narrow wirings described above referring to FIG. 2have been formed in a straight line form, they can be formed in acrooked line form. Such an example is illustrated referring to a wiringlayout diagram in FIG. 3. For simplicity of description, in the drawing,device regions, device separation regions, inter-layer insulation filmsand the like formed in or on a silicon substrate are omitted, and onlywirings are illustrated. In addition, the same component parts as thosedescribed above referring to FIG. 2 are denoted by the same symbols asused above.

As shown in FIG. 3, narrow wirings 25 and 26 formed in continuity orconnection with first wirings 21 and 22 so wide that W/V≧7 are formed,for example, in an L-shaped crooked form, and connection holes 48 and 49for connection to second wirings 31 and 33 are disposed at the tipportions of the crooked forms, respectively. In this case, also, it isnecessary to satisfy the relationship of W/S<143 μm⁻¹. This constitutionis effective in the case where a sufficient distance cannot be takenbetween the large-width first wiring and the connection hole.

In addition, as shown in FIG. 4, where a first wiring 21 is formed toextend in X direction, the narrow wiring 25 may be formed to extend in Ydirection from a side portion of the first wiring 21. Therefore, aconnection hole 48 is formed between the narrow wiring 25 and a secondwiring 31. Similarly, where a second wiring 22 is formed to extend in Xdirection, the narrow wiring 26 may be formed to extend in Y directionfrom a side portion of the second wiring 22. Therefore, a connectionhole 49 is formed between the narrow wiring 26 and a second wiring 33.In these cases, also, it is necessary to satisfy the relationships ofWs/V<7 and W/S<143 μm⁻¹, in the same manner as has been described abovereferring to FIG. 2.

In the above semiconductor device, as a countermeasure for coping withthe case where a connection hole cannot be disposed according to thewiring width, the second wiring is connected to a leader wiring portionwhich is formed in continuity with the first wiring and which is smallerin width than the first wiring, so that the problem which wouldotherwise be generated at the large-width wiring portion is obviated.The reason is the same as described above referring to FIGS. 11A and11B; specifically, by such a setting that W/S≦143 μm⁻¹, generation ofdefects can be obviated even with a single connection hole. In thiscase, it is necessary that the width Ws of the narrow wiring portionsmaller in width than the first wiring satisfies the relationship ofWs/V<7. The reason is as has been described above referring to FIG. 10.

In the next place, an embodiment of the method of manufacturing asemiconductor device according to the present invention will bedescribed referring to manufacturing step sectional views in FIGS. 5Aand 8B. In each of the manufacturing step diagrams, a section of theportion where the first wiring 21 and the second wiring 31 shown in FIG.1 above cross each other, taken along the arrangement direction of thesecond wiring 31, is shown. The same component parts as those describedreferring to FIG. 1 above are denoted by the same symbols as used above.

As shown in FIG. 5A, a first insulation film 12 covering a substrate 11provided, for example, with such devices as transistors, capacitors andthe like which are not shown is formed. By lithography technique andetching technique, wiring trenches 13 having a depth of 200 nm, forexample, are formed at portions where a first wiring layer is to beformed, of the first insulation film 13. Here, a wiring trench 13 w forforming a wide wiring and a wiring trench 13 n for forming a narrowwiring were formed.

Next, as shown in FIG. 5B, a barrier layer 14 is formed on the surfaceof the first insulation film 12 and on the inside surfaces of the wiringtrenches 13. The barrier layer 14 is formed, for example, by building upa tantalum (Ta) film in a thickness of 10 nm. Further, a copper (Cu)seed film 15 is formed, for example, by sputtering. The copper seed film15 is formed, for example, by building up copper in a thickness of 80nm. Next, electroplating is conducted to build up a copper (Cu) platinglayer 16 on the first insulation film 12 in a thickness of, for example,700 nm.

Subsequently, as shown in FIG. 5C, polishing by chemical mechanicalpolishing (hereinafter referred to as CMP) is conducted until thesurface of the first insulation film 12 is exposed, whereby surpluscopper and the barrier layer 14 on the surface of the first insulationfilm 12 are removed, leaving copper in the wiring trenches 13, with thebarrier layer 14 therebetween, resulting in that a first wiring 21 of afirst wiring layer is formed in the wiring trench 13 w and a firstwiring 23 is formed in the wiring trench 13 n. FIGS. 5A to 8B pertainingto the description here show the width-direction sections of the firstwirings 21 and 23. Of the first wirings formed in this manner, the firstwiring 21 is a large-width wiring which satisfies the relationship ofW/V≧7, where V is the diameter of the connection hole to be formedlater, and W is the width of the first wiring 21. The first wiring 23 isa wiring which satisfies the relationship of W/V<7, where V is thediameter of the connection hole to be described later, and W is thewidth of the first wiring 23.

Next, as shown in FIG. 6A, a copper diffusion preventive film 51covering the first wiring 21 is formed on the first insulation film 12.The diffusion preventive film 51 is formed, for example, by forming asilicon carbide (SiC) film in a thickness of 50 nm. Thereafter, a secondinsulation layer 52 in which to form a second wiring layer is formed ina thickness of, for example, 600 nm, by use of, for example, a siliconoxide-based material or a low-dielectric-constant insulating materialrepresented by polyaryl ether-based resins, silicon oxycarbide (SiOC) orthe like.

Subsequently, as shown in FIG. 6B, connection holes 41 and 42 reachingthe first wiring 21 are formed by lithography technique and etchingtechnique. In this case, it is desirable that the copper diffusionpreventive film 51 is at least left at the bottom portions of theconnection holes 41 and 42. In addition, the number of the connectionholes between the first wiring layer and the second wiring layer is onewhere W/V<7, is two where 7≦W/V<70, and is three where 70≦W/V, where Wis the width of the first wiring satisfying the relationship of W/V≧7,and V is the connection hole diameter. Besides, where a plurality ofconnection holes are formed for the first wiring 21 satisfying therelationship of W/V≧7, the connection holes are disposed at a connectionhole interval within the range of from 1 to 18 times the connectionhole. Incidentally, though not shown, a connection hole or holes forconnection to the first wiring 23 are also formed simultaneously withthe connection holes 41 and 42.

Next, as shown in FIG. 7A, a filling material 53 making it possible totake an etching selectivity ratio between itself and the secondinsulation film 52 is applied to fill up the connection holes 41 and 42by, for example, coating. In this case, the filling material 53 isformed also on the second insulation film 52. Thereafter, a resist isapplied onto the filling material 53, and a resist pattern 54 opened inthe region for forming a second wiring layer is formed by lithographytechnique.

Subsequently, with the resist pattern 54 as a mask, the filling material53 and the second insulation film 52 are processed by etching technique,to form wiring trenches (represented by a wiring trench 55 in thedrawing) for formation of the second wiring layer and to reopen theconnection holes for connection to the first wiring layer, as shown inFIG. 7B. In this case, the wiring trench 55 was processed to have adepth of 300 nm, for example. In the drawing, the connection holes 41and 42 reaching the first wiring 21 are shown. Though not shown, theconnection hole or holes reaching the first wiring 23 and a wiringtrench for connection to the connection hole or holes are also formedsimultaneously. In this instance, the diffusion preventive film 51formed at the bottom portions of the connection holes 41 and 42 are alsoremoved.

Next, as shown in FIG. 8A, for formation of the second wiring layer, abarrier layer 56 is formed on the inside surfaces of the wiring trench55, the inside surfaces of the connection holes 41 and 42, and on thesecond insulation film 52. The barrier layer 56 is formed, for example,by building up a tantalum (Ta) film in a thickness of 20 nm. Further, acopper (Cu) seed film 57 is formed, for example, by sputtering. Thecopper seed film 57 is formed by building up copper in a thickness of 80nm, for example. Next, electroplating is conducted to form a copper (Cu)plating layer 58 on the first insulation film 12 in a thickness of, forexample, 800 nm.

Subsequently, as shown in FIG. 8B, polishing by CMP technique isconducted until the surface of the second insulation film 52 is exposed,whereby surplus copper and the barrier layer 56 on the second insulationfilm 52 are removed, leaving copper in the wiring trench 55 and theconnection holes 41 and 42, to form a second wiring 31 of the secondwiring layer in the wiring trench 55 and in the connection holes 41 and42. The second wiring 31 formed in this manner satisfies therelationship of W/V<7, where V is the diameter of the connection holes41 and 42, and W is the width of the second wiring 31.

Thereafter, though not shown in the drawing, an insulation film and awiring layer are formed in the same manner as above-described, whereby amulti-layer wiring can be formed.

In the manufacturing method described referring to FIGS. 5A to 8B above,in the case of forming the leader wirings 25 and 26 described abovereferring to FIGS. 2 to 4, the leader wirings 25 and 26 smaller in widththan the first wirings 21 and 22 may be formed in continuity with thefirst wirings 21 and 22, together with the first wirings 21 and 22. Inthis case, paying attention to the first wiring 21, it is necessary tosatisfy relationship of Ws/V<7, where Ws is the width of the leaderwiring 25 and V is the diameter of the connection hole 48, and tosatisfy the relationship of W/S<143 μm⁻¹, where S is the area occupiedby the portion of the leader line 25 ranging from the first wiring 21 tothe location of the connection hole 48, and W is the width of the firstwiring 21 satisfying W/V≧7. In relation to the leader wiring 26 formedfor the second wiring 22, also, it is necessary to satisfy therelationships of W/S<7 and W/S<143 μm⁻¹.

In the above method of manufacturing a semiconductor device, althoughthe first wirings 21 and 22 are formed to be larger in width than thesecond wirings 31 and 33, the provision of the plurality of connectionholes 41 to 45 makes it possible to manufacture a semiconductor devicein which the probability of generation of defects at the connection holeportions is lowered. This is because the increase in the number ofconnection hole or holes ensures that where, for example, at least twoconnection holes are provided for connection between the wirings,breakage of electric conduction would not be generated unless defectsare generated simultaneously at two connection holes. Thus, theprovision of a plurality of connection holes is effective for preventingthe breakage trouble.

In addition, where the plurality of the connection holes 41 and 42 andthe connection holes 43 to 45 are provided, it is desirable that theconnection holes are disposed within predetermined connection intervals.The reason is as has been described referring to FIG. 9 above.

In the above-described method of manufacturing a semiconductor device,the number of the connection holes formed is one where W/V<7, is two,where 7≦W/V<70, and is three where 70≦W/V, where W is the width of thefirst wiring, and V is the diameter of the connection holes. Therefore,by disposing the plurality of connection holes according to the wiringwidth, it is possible to obviate the defects upon the high-temperaturestanding test, as has been described referring to FIG. 10 above.

Besides, even in the manufacturing method in which the leader wiringscontinuous with the first wirings and smaller in width then the firstwirings are formed and the connection holes are connected to the leaderwirings, the problem which would be generated at the large-width wiringportions is obviated. In addition, since the relationship of Ws/V<7 andthe relationship of W/V<143 μm⁻¹ are satisfied, the fraction defectiveupon the high-temperature standing test against W/S becomes zero (0), ashas been described above referring to FIGS. 11A and 11B.

While an example of forming the large-width wirings on the lower layerside has been described in each of the modes for carrying out thepresent invention, the present invention can be applied in the samemanner also to the case where the large-width wirings are provided onthe upper layer side.

As has been described above, according to the semiconductor device ofthe present invention, by such a setting as to regulate the number ofthe connection holes for connection to the large-width wirings and toregulate the locations of the connection holes according to the wiringwidth, the phenomenon of losing of Cu which would otherwise be generatedat the connection hole portions connected to the large-width wirings canbe obviated, so that it is possible to provide a semiconductor devicehigh in reliability. In addition, the two kinds of measures, i.e., themeasure relating to the number of the connection holes and the measurerelating to the side of the wirings for provision of the connectionholes, as a countermeasure against the losing of Cu at the connectionhole portions of the large-width wirings, produce the effect ofminimizing the restrictions to LSI designing.

According to the method of manufacturing a semiconductor device of thepresent invention, by such a setting as to regulate the number ofconnection holes for connection to large-width wirings and to regulatethe locations of the connection holes according to the wiring width, thephenomenon of losing of Cu which would otherwise be generated at theconnection hole portions connected to the large-width wirings can beobviated, so that it is possible to manufacture a semiconductor devicehigh in reliability. In addition, the two kinds of measures, i.e., themeasure relating to the number of the connection holes and the measurerelating to the side of the wirings for provision of the connectionholes, as countermeasure against the losing of Cu at the connectionholes portions of the large-width wirings, produce the effect ofminimizing the restrictions to LSI designing.

1. A semiconductor device comprising: a first wiring, an inter-layerinsulation film covering said first wiring, a connection hole or holesformed in said inter-layer insulation film so as to reach said firstwiring, and a second wiring connected to said first wiring through saidconnection hole or holes, said first wiring or said second wiring beingformed to be larger in width than the other wiring, wherein the minimumrequired number of said connection holes is one where W/V<7, is twowhere 7≦W/V<70, and is three where 70≦W/V, where W is the width of saidlarge-width wiring, and V is the diameter of said connection hole orholes.
 2. A semiconductor device comprising: a first wiring, aninter-layer insulation film covering said first wiring, a connectionhole or holes formed in said inter-layer insulation film so as to reachsaid first wiring, and a second wiring connected to said first wiringthrough said connection hole or holes, said first wiring or said secondwiring being formed to be larger in width than the other wiring, whereinsaid semiconductor device comprises a leader wiring formed incontinuation with said large-width wiring and smaller in width than saidlarge-width wiring, and said connection hole or holes are formed in saidinter-layer insulation film so as to reach said leader wiring.
 3. Thesemiconductor device according to claim 2, wherein the relationship ofWs/V<7 is satisfied, where Ws is the width of said leader wiring, and Vis the connection hole diameter, and the relationship of W/S<143 μ⁻¹ mis satisfied, where S is the area occupied by the leader wiring portionranging from said large-width wiring to the location of said connectionhole, and W is the width of said large-width wiring satisfying W/V≧7. 4.A method of manufacturing a semiconductor device, comprising the stepsof: forming a first wiring; forming an inter-layer insulation film onsaid first wiring; providing said inter-layer insulation film with aconnection hole or holes reaching said first wiring; and forming on saidinter-layer insulation film a second wiring connected to said firstwiring through the inside of said connection hole or holes, said firstwiring or said second wiring being formed to be larger in width than theother wiring, wherein the number of said connection hole or holes is onewhere W/V<7, is two where 7≦W/V<70, and is three where 70≦W/V, where Wis the width of said large-width wiring, and V is the connection holediameter.
 5. A method of manufacturing a semiconductor device,comprising the steps of: forming a first wiring; forming an inter-layerinsulation film on said first wiring; providing said inter-layerinsulation film with a single connection hole reaching said firstwiring; and forming on said inter-layer insulation film a second wiringconnected to said first wiring through the inside of said connectionhole, said first wiring or said second wiring being formed to be largerin width than the other wiring, wherein a leader wiring smaller in widththan said large-width wiring is formed in continuity with saidlarge-width wiring, together with said large-width wiring, and saidleader wiring is formed on said inter-layer insulation film so as to beconnected to said leader wiring through the inside of said connectionhole.
 6. The method of manufacturing a semiconductor device according toclaim 5, wherein the relationship of Ws/V<7 is satisfied, where Ws isthe width of said leader wiring, and V is the connection hole diameter,and the relationship of W/S<143 μm⁻¹ is satisfied, where S is the areaoccupied by the leader wiring portion ranging from said large-widthwiring to the location of said connection hole, and W is the width ofsaid large-width wiring satisfying W/V≧7.
 7. A semiconductor devicecomprising: a first wiring, an inter-layer insulation film covering saidfirst wiring, a connection hole or holes formed in said inter-layerinsulation film so as to reach said first wiring, and a second wiringconnected to said first wiring through said connection hole or holes,said first wiring or said second wiring being formed to be larger inwidth than the other wiring, wherein said semiconductor device comprisesa leader wiring formed in continuation with said large-width wiring andsmaller in width than said large-width wiring; and a plurality of saidconnection holes are provided at a connection hole interval within therange of from 1 to 18 times the connection hole diameter.
 8. Asemiconductor device comprising: a first wiring, an inter-layerinsulation film covering said first wiring, a connection hole or holesformed in said inter-layer insulation film so as to reach said firstwiring, and a second wiring connected to said first wiring through saidconnection hole or holes, said first wiring or said second wiring beingformed to be larger in width than the other wiring, wherein the minimumrequired number of said connection holes is one where W/V<7, is twowhere 7≦W/V<70, and is three where 70≦W/V, where W is the width of saidlarge-width wiring, and V is the diameter of said connection hole orholes, and wherein said plurality of connection holes are disposed at aconnection hole interval within the range of from 1 to 18 times theconnection hole diameter.
 9. A semiconductor device comprising: a firstwiring, an inter-layer insulation film covering said first wiring, aconnection hole or holes formed in said inter-layer insulation film soas to reach said first wiring, and a second wiring connected to saidfirst wiring through said connection hole or holes, said first wiring orsaid second wiring being formed to be larger in width than the otherwiring, wherein said semiconductor device comprises a leader wiringformed in continuation with said large-width wiring and smaller in widththat said large-width wiring; and wherein the minimum required number ofsaid connection holes is one where W/V<7, is two where 7≦WN<70, and isthree where 70≦W/V, where W is the width of said large-width wiring, andV is the diameter of said connection hole or holes and the relationshipof Ws/V<7 is satisfied, where Ws is the width of said leader wiring, andV is the connection hole diameter.
 10. The semiconductor deviceaccording to claim 9, wherein the relationship of W/S<143 μm⁻¹ issatisfied, where S is the area occupied by the leader wiring portionranging from said large-width wiring to the location of said connectionhole, and W is the width of said large-width wiring satisfying W/V≧7.11. A method of manufacturing a semiconductor device, comprising thesteps of: forming a first wiring; forming an inter-layer insulation filmon said first wiring; providing the inter-layer insulation film with aconnection hole or holes reaching said first wiring; and forming on theinter-layer insulation film a second wiring connected to said firstwiring through the inside of said connection hole or holes, said firstwiring or said second wiring being formed to be larger in width than theother wiring, forming a leader wiring smaller in width than saidlarge-width wiring in continuity with said large width wiring, togetherwith said large-width wiring, wherein a plurality of said connectionholes reaching said large-width wiring are provided at a connection holeinterval within the range of from 1 to 18 times the connection holediameter and the number of said connection hole or holes is one whereW/V<7, is two where 7≦W/V<70, and is three where 70≦W/V, where W is thewidth of said large-width wiring, and V is the connection hole diameter.12. A method of manufacturing a semiconductor device, comprising thesteps of: forming a first wiring; forming an inter-layer insulation filmon said first wiring; providing said inter-layer insulation film with asingle connection hole reaching said first wiring; and forming on saidinter-layer insulation film a second wiring connected to said firstwiring through the inside of said connection hole, said first wiring orsaid second wiring being formed to be larger in width than the otherwiring, wherein a leader wiring smaller in width than said large-widthwiring is formed in continuity with said large-width wiring, togetherwith said large-width wiring, and said leader wiring is formed on saidinter-layer insulation film so as to be connected to said leader wiringthrough the inside of said connection hole, and wherein the relationshipof Ws/V<7 is satisfied, where Ws is the width of said leader wiring, andV is the connection hole diameter, and the relationship of W/S<143 μm⁻¹is satisfied, where S is the area occupied by the leader wiring portionranging from said large-width wiring to the location of said connectionhole, and W is the width of said large-width wiring satisfying W/V≧7.